Do you think there should be free, open instructionset architecture (ISA) justlike we have free, open networking standards and free, open operatingsystems? Do you think the best architectural style for any free, open ISA is RISC? Do you want to hear more about these issues? Then join the next Silicon Valley IoT Meetup on October 27, 2015, in Mountain View, CA.
For our last Meetup of the year, our presenter isProfessor Krste Asanovi from the EECS Department at the Universityof California, Berkeley. He will lead a discussionaboutthe RISC-V Instruction Set Architecture, opensourceISAs, and IoT.
What Is RISC-V?
RISC-V (pronounced "risk-five") is a new instruction set architecture that was originally designed to support computer architecture research and education, and it could become a standard open architecture for industry implementations. RISC-V was first developed in the EECS Department at UC Berkeley. Professor Asanovi leads the free RISC-V ISA project, is chairman of the RISC-V Foundation, and has recently co-founded SiFive Inc. to support commercial use of RISC-V processors. You can learn more about RISC-V here.
RSVP for the Meetup
To attend this Meetup on the topic, "Instruction Sets Should Be Free: The Case For RISC-V," please RSVP at our Meetup page. The event takes place on Tuesday, October 27, and starts at 6:30pm.
We're also happy to announce a raffle giveaway. Three lucky attendees will win a three-month package of free Neo connectivity ($25 value) for your IoT devices. Make sure you stay for the drawing.Hope to see you there!